Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device including a side-junction, and a method for fabricating the semiconductor device.
When cells having a vertical transistor structure employ buried bit lines (BBL), each buried bit line BBL may be adjacent to two cells. For a cell to be driven by a buried bit line BBL, a One-Side-Contact (OSC) process may be performed for forming a contact in an active region while insulating another active region. Hereafter, the OSC process will be simply referred to as a sidewall contact process. In a cell of a vertical transistor structure formed by using the sidewall contact process, each active region includes a body isolated by a trench and a pillar formed over the body. A buried bit line BBL fills a trench between bodies, and a word line (or a vertical gate) is disposed adjacent to the sidewall of a pillar and extended in a direction crossing a buried bit line BBL. The word line forms a channel in a vertical direction.
According to the sidewall contact process, a portion of a sidewall of the body is exposed to couple an active region with a buried bit line BBL. Then, a junction is formed by implanting or diffusing a dopant into the exposed portion of the sidewall of the body. The buried bit line BBL and the body are electrically coupled through the junction. Since the junction is formed on just one sidewall of the body, the junction is referred to as a One-Side Junction (OSJ).
When a diffusion barrier is formed between the buried bit line BBL and the side junction, agglomeration may be caused. To address such a concern, a method of forming a one-side junction by directly forming a doped polysilicon layer without forming a diffusion barrier has been researched.
FIGS. 1A to 1C are cross-sectional views illustrating a conventional method for forming a semiconductor device by using a sidewall contact process.
Referring to FIG. 1A, a plurality of bodies 103 isolated by trenches 102 are formed over a substrate 101. A hard mask pattern 104 is formed over the bodies 103. The hard mask pattern 104 functions as an etch barrier during the formation of active regions.
An insulation layer is formed on both sidewalls of each body 103, the surface of the substrate 101 between the bodies 103, and the surface of the hard mask pattern 104. The insulation layer includes a liner oxide layer 105 and a liner nitride layer 106.
A sidewall contact 107 is formed by removing a portion of the insulation layer. The sidewall contact 107 is a one-side contact which exposes a portion of just one sidewall of a body 103.
Referring to FIG. 1B, a doped polysilicon layer 108 is formed over the substrate structure to gap-fill sidewall contacts 107 and the trenches 102. Here, the doped polysilicon layer 108 is doped with a dopant for forming a sidewall contact. For example, the dopant doping the doped polysilicon layer 108 may be an N-type impurity, such as phosphorus (P).
Referring to FIG. 1C, the doped polysilicon layer 108 is planarized and etched back. As a result, the doped polysilicon layer pattern which is obtained from the planarization and etch-back processes gap-fills a portion of each trench 102 to the degree that the doped polysilicon layer pattern has a height to at least contact the sidewall.
Subsequently, an annealing process 109 is performed. Here, the dopant doping the doped polysilicon layer pattern is diffused into the sidewall of the body 103 exposed by the sidewall so as to form a sidewall junction 110.
However, when the dopant is excessively diffused during the process of forming the doped polysilicon layer pattern, a floating body 111 may be generated to increase a potential and cause a concern with respect to the operation of a cell transistor, such as a threshold voltage drop.